Area Efficient Full Subtractor Based on Static 125nm CMOS Technology

K. Gopi; P. Gowtham | G. Naveen Balaji; G. Hemanth Kumar

Title:
Area Efficient Full Subtractor Based on Static 125nm CMOS Technology

Authors:
G. Hemanth Kumar | K. Gopi | P. Gowtham | G. Naveen Balaji
DOI:
https://doi.org/10.31142/ijtsrd18860

Cite This Article :

G. Hemanth Kumar | K. Gopi | P. Gowtham | G. Naveen Balaji "Area Efficient Full Subtractor Based on Static 125nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-6, October 2018, pp.1371-1374, URL: https://www.ijtsrd.com/papers/ijtsrd18860.pdf

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Abstract :
A combinational logic circuit is said to be independent of time since it gives the results based on present input not past input. This research is concerned about the comparison between currently existing full subtractor IC and the subtractor which is built efficiently in the 125nm and observing the distortion and changes caused in the result of both full subtractor. The behaviour of the efficient full subtractor is designed using tanner eda tools which was useful and the currently existing full subtractor is designed using xilnx software and lastly the layout for this research is designed with the help of multisim. With help of this research many newly created circuits can designed much more smaller.

Keywords :
Full Subtractor, cmos, static CMOS, 125nm, tanner, multisim, Xilinx, half subtractor

Publication Details:

Unique Identification Number : IJTSRD18860

Published In : Volume-2 | Issue-6, October 2018

Page Number(s) : 1371-1374

Publisher Name : IJTSRD | www.ijtsrd.com | E-ISSN 2456-6470

Copyright © 2019 by author(s) and International Journal of Trend in Scientific Research and Development Journal. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0) (http://creativecommons.org/licenses/by/4.0)

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